1. Field of the Invention
The present invention relates generally to a dual apparatus having two systems which operate in active (ACT) state and standby (SBY) state respectively. Especially, the present invention relates to the switching between the systems of the dual apparatus and to clock control therefor.
2. Description of Related Art
A switching system for example has a dual system configuration in which two equally configured systems, system 0 and system 1 for example, operate to ensure continued service provision if a fault is encountered. In such a dual system, one system operates in active mode while the other in standby mode. A switching system based on such a dual configuration comprises a CPR (Call PRocessor), a PSA (Processor Access Controller (PAC) and System Bus Arbiter), LRPCS (Line/Register signal and Path Controller for Small switch), TSW (Time SWitch), TNG (ToNe Generator), HWINF (HighWay INterFace), SGC (SiGnaling Controller), LTC (Line Trunk Common), DT (Digital Terminal), and SAMSH (Synchronization and Alarm Maintenance SHelf), each being arranged for each of the two systems. A dual apparatus based on system 0 and system 1 may be configured such that a single device constitutes the ACT/SBY system as with the CPR or plural units like LRPCS, TSW, and HW for example constitute one ACT/SBY system. Continued service provision requires switching between the ACT system and the SBY system when a fault is detected or maintenance is made in the ACT system in the above-mentioned configuration unit of the ACT/SBY system.
Control for switching between the ACT and SBY systems is made such that one (LRPCS for example) of the dual devices constituting each ACT/SBY system sends an ACT/SBY specification signal and an ACT/SBY select result signal to the other system through a confounding line connected to a dual device (LRPCS for example) of the other system to check the state of the other system, thereby preventing both the systems from becoming the ACT system or the SBY system at the same time. The ACT/SBY specification signal indicates the active state or the standby state specified by an upper unit such as a CPR or specified externally. The ACT/SBY select result signal transmits the ACT/SBY selection result of the dual apparatus to the other system by considering the specification signals of the current system and the other system, the current ACT/SBY state of the dual apparatus, and the fault occurrence status of the other system. For example, if the power supply of the system 0 of the dual apparatus fails when the system 0 is active and the system 1 is standby, then the system 1 detects the fault of the system 0 and, in order to shift to the active state, sets the ACT/SBY select result signal to the active state, and sends this signal to the system 0. The system 0, which is active, informs the system 1 that the ACT/SBY select result signal is active. The system 1, because the selection results of the system 0 and the system 1 are active, maintains the standby state so far set. If the system 0 cannot drive the ACT select result signal due to power failure, the system 1 selects the active state and shifts to the active state.
On the other hand, the SGC receives a clock indicative of an 8-KHz frame, a specification signal indicative of one of ACT and SBY states, and a control signal for controlling call origination and termination from the dual LRPCS through the TSW. By use of the highway interface circuit, the SGC separates the clock and specification signal supplied from the system-0 and system-1 LRPCSs from the predetermined highway time slots. The SGC, in phase-synchronization with the 8-KHz clock of the ACT system specified by the specification signal through the PLO (Phase-Locked Oscillator) installed on the highway interface circuit, supplies the 32-MHz clock and the 8-KHz clock obtained by dividing the 32-MHz clock to other internal circuits as operating clocks. The other internal circuits of the SGC execute HDLC data transfer and LAPD communication in synchronization with the 32-MHz and 8-KHz operating clocks supplied from the PLO.
However, the above-mentioned related-art dual apparatus involves the following problems:
(1) Conventionally, if the power supply for supplying power to the LRPCS and other units fails, the ACT specification of the failing side is maintained until the ACT/SBY select signal cannot be driven due to the lowered voltage of the failing LRPCS. Therefore, ACT-system switching is made when the failing system circuit operates no more. At this point of time, because the circuit does not operate normally, the transmission of signals such as clocks to the lower units such as the SGC is discontinued. Consequently, service provision is discontinued on the lower units. If the voltage level on the ACT side lowers temporarily for some reason, putting that device out of its operation guaranteed range, that device may not operate normally, failing to send normal signals to the lower units. In such a situation, no system switching is executed.
(2) The SGC for example receives a highway frame-mapped specification signal indicative of ACT or SBY state supplied from an upper unit such as the LRPCS and generates, through the PLO, as an operating clock, a clock (32 MHz) synchronized with the reference clock mapped into the highway frame time slot of the ACT system indicated by the specification signal. However, if the ACT-system clock fails, deviating the period of the reference clock or stopping the reference clock, the PLO gets out of synchronization with the reference clock, interrupting communication during that period.
In addition, if the ACT-system fault is immediately detected by the LRPCS, causing ACT/SBY system switching, the PLO outputs an out-of-synchronization alarm because the specification signal is supplied through the highway time slot and, depending on the system switching timing, if the specification signal is supplied immediately before fault occurs, the system switching is notified through the time slot of the next frame, thereby delaying system switching recognition. Once out-of-synchronization occurs, it takes a certain time to restore synchronization. If this time is long, the LAPD communication link may not be maintained, failing continued service provision. Further, it is also a problem that an out-of-synchronization alarm issued when the lower unit itself is not failing causes system-switching fault processing. Prevention of such a problem requires the measures for preventing the alarm from being issued by the lower unit for the fault of the upper unit.
It is therefore an object of the present invention to provide a dual apparatus for quickly executing system switching without adversely affecting lower units when a fault occurs in the ACT system.
It is another object of the present invention to provide a highway interface circuit that does not cause out-of-synchronization even if clock fault occurs.
In accordance with an aspect of the present invention, there is provided a dual apparatus having a first unit and a second unit of a same configuration, one being operated in an active state while the other in a standby state. Each of these first and second units comprises a first selector for setting a current unit to a first active state if a predetermined fault occurs in the other unit; a second selector for setting the current unit to the active state if a predetermined fault occurs in the other unit and the first selector selects the first active unit, and sending information indicative thereof to the other unit and, setting the current unit to the standby state if the predetermined fault does not take place in the other unit and the first selector selects the active state and a state indicated by information supplied from the other unit is the active state, and sending information indicative thereof to the other unit; and a register for holding one of the active and standby states selected by the second selector.
In accordance with another aspect of the present invention, there is provided a highway interface circuit for generating a first clock on the basis of a reference clock supplied from a highway, comprising: a selector for selecting one of the reference clock and a free-running clock on the basis of a switch signal to output a second clock; a phase-locked oscillator, synchronized with the second clock, for generating the first clock having a frequency which is an integral multiple of a frequency of the second clock; a free-running clock generator, reset on the basis of the switch signal and the reference clock, for executing a counting operation on the basis of the first clock to generate the free-running clock having a same frequency as that of the reference clock; and a reference clock monitor for executing a counting operation on the basis of the first clock to generate the switch signal indicative of abnormalcy in the reference clock.
The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent, and the invention itself will best be understood from a study of the following description and appended claims with reference to the attached drawings showing some preferred embodiments of the invention.